It is known in the art of digital signal processing to use memory devices as functional elements. The memory device is programmed at respective memory locations with values corresponding to address values transformed by a desired transfer function. For example, if it is desired to scale a digital signal by a particular value, each memory location is programmed with a value equal to the address of the particular memory location multiplied by the scaling value. The system may be made adaptive by segmenting the memory device into tables, each of which corresponds to the address values being multiplied by a different scale factor. The particular table utilized at any given time is accessed by appending control bits to the address codes.
Not all transfer functions can be realized with memory elements in a cost effective manner. Conversely, some transfer functions can only be realized using programmed memories. This is particularly true for certain non-linear functions. Unfortunately the memory devices may become undesirably large. Consider for example an adaptive system processing 8-bit samples, a memory with 8-bit precision, and 8-bit adaptive control signals. The required memory includes 2.sup.8 tables having 2.sup.8 memory locations of 8 bits each or a total memory capacity of 524,288 bits. A memory of this size will impose appreciable cost to the system.
The present inventor realized that for certain families of transfer functions that are implemented in adaptive systems, the memory requirements may be significantly reduced. This is achieved by storing values corresponding to only one representative transfer function in memory. Then by appropriately offsetting the signal applied to the memory and scaling the values provided by the memory, responses corresponding to others of the family of transfer functions may be effectively realized.